1. Field of the Invention
The present invention relates to system the internal data movement within a system and more particularly, to the use of adaptive synchronization in storage systems.
2. Description of the Related Art
In modern computer systems, a storage system typically has an external interface that consists of a storage interconnect chip running a relatively small amount of firmware or microcode. Higher level software executed by a central processing unit (CPU) of the storage system manages the interconnect chip. This chip has the primary responsibility of enabling and interfacing with the external connectivity to a host from the storage system. The high level software running inside the storage system interacts with the interconnect chip to receive incoming commands, perform data transfers, and receive status notifications.
The storage interconnect chips are experiencing tremendous demands in regards to the speed of the link provided by the interconnect chips between the host and the storage system. In order to be able to operate at the interconnect chip's maximum capability, the communication between the interconnect chip and the higher level software running in the CPU of the storage system needs to be very efficient, otherwise the overall performance of the storage system suffers. Unfortunately, current techniques in interfacing the higher level system software and the interconnect chip fall short of meeting the increasingly demanding input/output (I/O) requirements at higher link speeds. Studies have shown that the synchronization mechanisms currently used between the system software and the interconnect chip cause considerable delays as discussed in more detail below.
FIG. 1 illustrates a standard storage sub-system 10. The storage sub-system 10 provides a communication path between storage area network (SAN) 18 and storage devices 22a and 22b. Interconnect chips 12 and 14, also referred to as a front end port and a back end port, respectively, are in communication with CPU 16. The front end port 12 is in communication with a storage area network (SAN) 18, which in turn communicates with the hosts 20a and 20b. The back end port 14 is in communication with storage devices 22a and 22b. 
Typically, the communication protocol between the system software executed by the CPU 16 is configured such that for each command or status notification sent from the front end port 12 to the CPU 16, the CPU 16 is interrupted. This configuration holds true for communication from the back end port 14 to the CPU 16. It should be appreciated that interrupts for each and every command or status notification can be taxing when there are a large number of commands to be processed. Consequently, for every data transfer request there may be two interrupts generated (e.g., one interrupt for the command arrival and one interrupt for the status notification). Such an overload of interrupts can greatly reduce the I/O throughput. Thus, where interrupts exist for each and every command all other activity within the system is stalled as the interrupt handler is continually pulling out incoming commands. Another technique for managing the interrupts, collects as many commands and status notifications as possible and then interrupts the CPU to process all of the collected commands and status notifications. Collecting as many commands and status notifications leads to excessive bursts in performance of the storage system, not to mention the burden placed on the software for the collection and bundling of the commands and status notifications. In either case, the interrupts used are excessive either in quantity or the amount of time spent processing them, therefore, the system does not transfer data at a maximum or near maximum capability.
Another shortcoming of the configuration of FIG. 1 is that the communication channels between front end port 12 and the CPU 16 are not intelligently utilized. For example, where a maximum amount of commands are collected for the CPU 16, an interrupt is issued for the CPU to pick up the collected commands. However, front end port 12 is unable to post additional commands until the front end port receives notification that the CPU 16 has completed processing of all of the collected commands. Accordingly, the latency of the system is adversely impacted from this scheme.
In view of the foregoing, there is a need for a more efficient method of communication between the CPU/software and the interconnect chip (e.g., front end port, back end port) that maximizes the I/O throughput to the full capability of the interconnect chip.